Low density parity code (LDPC) decoder systems are current generation iterative soft-input forward error correction (FEC) decoder systems that have found increasing popularity in FEC applications where low error floor and high error correction performance are desired. LDPC codes are defined in terms of a two-dimensional parity-check matrix, referred to as an H matrix, that represents a set of parity check equations such that cH=0 where c is a codeword of the LDPC code.
A sub-class of LDPC codes is quasi-cyclic LDPC (QC-LDPC) codes. In an H matrix of a QC-LDPC code, each matrix value represents a Q×Q circulant matrix, and a codeword comprises circulants of Q bits.
In a layered QC-LDPC decoder, soft information elements of each circulant stored in a memory is read and input to a layer processor, beginning from a starting soft information element determined by the H matrix and incremented sequentially until the entire content of the memory is input to the layer processor. The updated soft information elements output by the layer processor is written back to the memory over the original soft information.
Improvements to QC-LDPC decoders are desired.